Division logic circuit

ABSTRACT

Division logic circuit for measuring the amount of displacement such as in length and angle by counting pulses each corresponding to a finely divided unit in length or angle by an electronic counter. A pulse is generated at the rise or descent of each pulse in one of a plurality of specifically quantized signals determined in relation to the variation in the amount of displacement so as to be counted by the electronic counter, and discriminating circuits generate output signals each indicative of the specific combination of the conditions of all the quantized signals thereby permitting the displacement corresponding to a finely divided unit in length or angle to be detected so that the displacement to be measured is digitally counted by using the above two kinds of signals at a speed higher than the maximum response speed of the electronic counter.

Umted States Patent [1 1 [111 3,749,890 Kamachi 1 July 31, 1973 DIVISION LOGIC CIRCUIT Primary Examiner-Maynard R; Wilbur [75] lnventor: Shin-ichi Kamachi, Tokyo, Japan Assmam Examiner joseph Thesz' Att0mey--l-lans Berman [73] Assignee: Olympus Optical Co., Ltd., Tokyo, Japan 571 ABSTRACT [22] Filed: June 21, 1971 Division logic circuit for measuring the amount of displacement such as in length and angle by counting [21] Appl pulses each corresponding to a finely divided unit in i i 7 length or angle by an electronic counter. A pulse is gen- [52] U.S. Cl...'..'.. 235/92 CP, 235/154, 235/92 CV, erated at the rise or descent of each p l nq 9f? 1 Y 235/92R; 235/92.SH plurality of specifically q'uantized signalsdeter'minedin; 1 j z [51] Int. Cl. .t H03k 13/24 relation to the variation in the amount of displacement [58] Field of Search.....@ 235/92 CA, 92 LG, 80 as to be counted by the electronic counter, and dis- 235/92 CP, 92 CV, 92 SH, 154 criminating circuits generate output signals each indicative of the specific combination of the conditions of all [56] References Cited the quantized signals thereby permitting the displace- UNITED STATES PATENTS ment corresponding to a finely divided unit in length or 2 954 165 9/1960 M ers v 235/92 CP angle to be detected so that the displacement to be 3 213 268 10/1965 En ersiit lliIIIIIIIIIII.... 235/154 measured is digitally by Sing the abme FPS RESET SIGNAL kinds of signals at a speed higher than the maximum response speed of the electronic counter.

2 Claims, 22 Drawing Figures SS POSITIVE, NEGATIVE SIGN IN- PUT PATENIEDJULB 1 I915 3.749.890

' sum 03M 14 FFI FF 5 s, s

POSITIVE,

' r NEGATIVE RESET SIGNAL SIGN PUT INVENTOR Sh/n 4% 1' ka 'q l ja /V75 PAIENIEDJULIN I975 7 9, 90

S LOGIC 1" WHEN POSITIVE LOGIC 0 WHEN NEGATIVE OUTPUT D9 FROM DISCRIMINATING CIRCuIT R ZERO C 9 ADDITION DELAY DETECTING CIRCUIT AND M R D-Q CIRCuIT v I S Q S Z I FF6 TI N EEQJ'R 0 e SUBTRACTION DEF INVENTOR 11 KGMQ L @5044, nae 5,

AGENT;

PAIEIIIEIIIII s 3.749.890

' SHEET U70F14 (1 ZERO DETEC- TION SIGNAL OUTPUT OP I I b. BELAY OIRcUIT C OUTPUT D9 IN ADDITION OUTPUT OF d. ANDH IN ADDITION OUTPUT OF A e DIFFERENTIA- TION CIRCUIT DEF I I v I OUTPUT OF {FLIP-FLOP I FF6 IN ADDITION OUTPUT S ISSUED g OUTPUT D9 IN SUBTRACTION OUTPUT OF h. ANDII IN SUBTRACTION OUTPUT ISSUED INVENTOR w-lc" Kommc/ m w cam 1 YPAIENIEDJIILSI I923 I. OUTPUT OF ANDB sum 080F111;

OUTPUT D9 FROM 0 DELAY b ADDITION CRIMINATING CIRCUIT ANDIZ SHIFT-UP cIRcuIT R PULSE DaI OUTPUT DO SUBTRAC- FROM DIS- DELAY" ANDI3 -TION CRlMINATING C CIRCUIT d I 'U CIRCUIT R PULSE Hg. /4 ADDITION OUTPUT D9 FROM G'DISCRIMINATING CIRCUIT R b. OUTPUT OF DELAY CIRCUIT D2 I I OUTPUT DO FROM 1 'DISCRIMINATING vI I2 CIRCUIT R. d. OUTPUT OF DELAY CIRCUIT D3 ADDITION e. OUTPUT OF AND|2 I SHIFFUP PULSE I NVENTOR Kanc4 1' PAIENIEU JUl. 3 1 Ian sum 10 or INVENTOR 56m- (C4; Kama 64/ PATENIEB JULB 1 I973 3.749.890

SHEET '13'IIF I I WEIGHT COUNTING W(P) I L9 CIRCUIT w c c DECIMAL p Y ADDITION gab CIRCUIT I D A c 01 8 CONVERSION J CIRCUIT I FCC H 20 PM "LI IOI WHEN PM=| o ---oL2 LOGIC 0' I 4,I 000 WHEN PM=O WEIGHT F/ p... cgI m Tl N e g 2/ u we 0 1 DECIMAL COMPLEMj-ZNT *1 C(QISVEESION I I CIRCUIT CIRCUIT 5 J- D A C N c C CONVERSION CIRCUIT F C C I SIGN INPUT /Qdmm (Mo/ PATIENIELI 3.749.890 SHEET 1; 0F 14 Fig. 22

9D! CDINCIDENCE ANDII 0 DELECTIIING Om f CI CU AND I Ob I2 D2 CDINCIDENCE 'ANDI3 DETECTING I bm CIRCUIT ANDM bBC C CD3 v CDINCIDENCE ANDIS DETECTING Cm CIRCUIT ANDG d o CD4 d I I CoINCIDENCE ANDI? DETECTING dm CIRCUIT iAND 8 CPS (1656 L CD NcgDEN C E WANDIQ D T CTI M em G CIRCUIT H ANDZO DIVISION LOGIC CIRCUIT BACKGROUND OF THE INVENTION The present invention relates to a division logic circuit and, more particularly, to a logic circuit by which the amount of displacement such as in length and angle represented by electric pulses can be measured by using counting means, wherein the measuring speed is made higher than the maximum response speed of the counting means.

A digital counting system was well known in which a displacement such as in length and angle is measured digitally by a measuring-instrument utilizing moire fringes or magnetic grating.

As a counting method in which the displacement is measured by counting the number of finely divided units in length or angle, the number being indicative of the displacement, it has been the practice to produce an electric pulse signal for each displacement by one finely divided unit in length or angle and counting the number of the pulse signals corresponding to the displacement to be measured by using an electronic counter.

In such a method, however, the speed at which the displacement by one unit can'be counted and indicated by the electronic counter is limited by the maximum response speed thereof, for example, in the order of 100,000 pulses/sec. Therefore, when the finely divided unit is set to be l/l0,000"", the maximum counting speed is limited to mm/sec.

The present invention aims at providing a division logic circuit by which the maximum counting speed is not limited to the maximum response speed-of the electronic counter thereby permitting the counting speed to be raised for higher than the conventional electronic counting system.

SUMMARY OF THE INVENTION The object of the present invention is to provide a novel and useful division logic circuit by which the amount of displacement such as in length and angle represented by electric pulses can be measured by an electronic counter at a speed substantially higher than the maximum response speed of the counter.

The object of the present invention is achieved by the provision of a division logic circuit in which, instead of generating one electric pulse for each'displacement by one unit, a pulse is generated at the rise or descent of each pulse in one of a plurality of specifically quantized signals determined in relation to the variation in the amount of displacement so as to be counted by an electronic counter, while discriminating circuits generate 7 output signals each indicative of the specific combination of the conditions of all the quantized signals thereby permitting the displacement by one finely divided unit to be detected so that the displacement to be measured is digitally counted by using the. above two kinds of signals at a speed higher than the maximum response speed of the counter.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing the method for detecting the brightand dark areas in moire fringes in a measuring instrument utilizing moire fringes;

FIG. 2 is a diagram showing a process of obtaining the measured value by using the condition of the combination of the detecting signals;

FIG. 3 is a diagram showing the relationship between the condition of the combination of the detecting signals and the amount of displacement;-

FIG. 4 is a table showing the principle of the operation of the division logic circuit of the present invention;

FIG. 5 is a diagram showing Boole bundle for explaining the principle of the present invention;

FIG. 6 is a block diagram showing an embodiment of the electric circuit of the division logic circuit of the present invention;

FIG. 7 is a block diagram showing an embodiment of i the .cyclictransposition circuit used in the pres'ent .in.-.. I v

FIG. 8 is a block transposition circuit for effecting a single transposition;

FIG. 9 is a diagram showing detailed construction of of the circuit for generating addition or subtraction shift-up pulse;

FIG. 14 is a diagram showing various pulse signals for explaining the operation of the circuit of FIG. 13; FIG. 15'is a diagram showing anembodiment of the vtransposition'circuit used in the present invention;

FIG. 16 is a diagram showing the positions of the marking bits in another embodiment of the division logic circuit of the present invention;

FIG. 17 is a block diagram showing the embodiment of the electric circuit of the division logic circuit using the marking bits shown in FIG. 16;

FIG. 18 is a diagram showing an embodiment of the weight counting circuit used in the logic circuit of FIG. 17; 1

FIG. 19 is a block diagram showing an embodiment of the bit conversion and display circuits used in the logic circuit of FIG. 17;

FIG. 20 is a diagram showing an embodiment of 5 con-version circuit used in the bit' conversion circuit of FIG. 19;

FIG. 21 is a block diagram showing another embodiment of the bit conversion and display circuits in the logic circuit of FIG. 17; and

FIG. 22 is a diagram showing an embodiment of the marking bit position designating circuit used in the logic circuit of FIG. 17.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS X-X'. Assuming that one cycle of the moire fringe is diagram showing thesing'le cyclic 217 and the distance between the adjacent two photoelectric elements P --P is rr/S, the output signals obtained from the respective photoelectric elements P P as the moire fringes are displaced in the direction of X-X' will have a phase difference of 11/5 between the output signals of the adjacent two of photoelectric elements P -P Therefore, when these output signals are applied to Schmitt trigger circuits, respective, for example, quantized signals aare obtained as shown by A- E in FIG. 2, a phase difference of 11/5 existing between the adjacent two of signals a-e. Various methods other than that using moire fringes were known to obtain a plurality of detecting signals having a certain phase difference between the adjacent two of the signals by using a plurality of detecting devices or by using various well known phase dividing systems, for example. 7

When pulse signals are generated at the rise and the descent of each of these five signals a-e by using differentiation circuits and these pulse signals are supplied to an or" circuit, for example, to obtain a single output, the output of the or" circuit is indicated by F in FIG. 2.

In the prior art method for measuring the displacement by using the pulses, the output F has been counted by an electronic counter. As described previously, the maximum counting speed is limited by the maximum response speed of the electronic counter.

In order to eliminate the above disadvantage of the prior art, the present inventor has proposed a method in which, instead of generating a pulse signal for each unit displacement, a pulse signal is generated at the rise or descent of one of the specifically quantized signals ae as shown by J in FIG. 2 which is produced at the descent of the signal e so as to be counted by an electronic counter, and discriminating circuits are provided which discriminate the specifically set combination of the conditions of the quantized signals a-e thereby producing signals G-I as the outputs thereof so that they are used to detect the displacement by one finely divided unit, thus permitting the displacement to be measured to be counted by the above two kinds of signals.

In such a counting system, each of the displacements represented by to 9 units, respectively, can be indicated by the specific combination of the condition of the five quantized signals a-e as shown in FIG. 3. The displacement beyond 9 units can be indicated by the indication of the electronic counter which is counting the output pulses J shown in FIG. 2 in combination with the indication given by the specific combination of the five quantized signals a-e shown in FIG. 3. In other words, when all the quantized signals a-e are in lower level, i.e., 0 condition, and the zero point is set at the condition in which all the quantized signals a-e are in lower level, the displacement by one unit can be indicated when only the signal a is changed to higher level, i.e., 1 condition, while the remaining four signals b-e are kept in lower level. In like manner, when the signal b is changed to higher level, the displacement by two units is indicated. Thus, the number of units by which the displacement is represented is indicated by the successive change in the condition of either of the five quantized signals a-e. When the number of units reaches 10, the indication of unit in FIG. 3 returns to 0. Therefore, when one unit is to be counted as l in the electronic counter, the lowest or last figure in the number is indicated by discriminating the specific combination of the conditions of the signals a-e, while the second to last figure in the-number and the higher fig ure in the number can be indicated by generating pulse at the descent of the signal e as shown by J in FIG. 2 so as to be counted in the electronic counter. There fore, the counter is required to merely count one pulse for the displacement of IO units. Thus, the speed at which the displacement by one unit is indicated in this method can be made 10 times higher than the maxi mum response speed of the electronic counter.

In the above embodiment, five photoelectric elements P -P are used so as to producefive quantized signals a-e. However, the number of .the photoelectric elements can be changed optionally.' For example,

when four photoelectric elements are used, the last figure in the number is indicated by 0-7 units instead of 0-9 units.

In a digital measuring instrument, it is in general desirable to allow'the origin of the measurement to be set to any optional point or any of 0-9 units shown in FIG. 3 so as to permit the amount of the displacement from the thus set origin to be counted and displayed. In a prior counting device in which only the pulse signals are counted, the origin can be freely set to any optional point by merely resetting the electronic counter at the set origin. In the system in which the last digit in-the number is indicated by the specific combination of the conditions of the signals a-e as described above, no problem arises when the origin is set at the unit 0 at which all the signals a-e are made zero, because the discriminating circuit indicates the selected one of the units 0-9 by discriminating the predetermined combination of the conditions of the signals a-e. If, however, the origin is set to any of the 1-9 units other than 0 unit, the indication of the last digit in the number can not be made zero by merely resetting the electronic counter.

' The present invention avoids the above described difficulty and provides a division logic circuit by which correct measured value of the displacement from the origin is obtained even though the origin is set to any of the units O-9 or any combination of the conditions of the. signals a-e.

The present invention comprises a division logic circuit wherein an amount or quantity represented by the specific combination of the conditions of a plurality of signals the condition of only one of which is changed at a time is converted to an amount or quantity measured from an origin selected at an optional combination of the conditions of the signals, the logic circuit being characterized by a memory circuit for memorizing the combination of the conditions of the signals to be set as an origin, a parity circuit for producing exclusive or outputs of the corresponding sets in the combination of the conditions of the signals memorized in the memory circuit and in the combination of the conditions of the signals to be converted so as to give the amount of quantity measured from the set origin, respectively, a cyclic transposition or substitution circuit for effecting cyclic transposition in the combination of the conditions of the signals in regular order of the combination of the outputs of the parity circuit, and a control circuit for producing control signal from the combination of the conditions of the signals memorized in the memory circuit was to actuate the cyclic transposition or substitution circuit. a i

Now, referring to FIG. 4, five signals a, b, c, d and e are used for producing 10 units 0 to 9 by the coding of parity vectorlP is represented by the combination of the conditions of the signals a to e.

Such a coding of the combination is represented by five such a Boolean lattice the indication of the last digit in the counted number is made at the origin, if the origin is set to the code (00000). When an optional point, the code (001 l l for example, is set to the origin, however, the indication of the last figure in the number at the origin is not 0 but is made 3" unit.

Therefore, in order to be able to select the reset position at any optional point or the code, conversion of the coding must be effected which is equivalent to the rotation of Boolean lattice by an appropriate distance depending upon the selected reset position. Thus, when the code (OOl l l) is selected as the origin, the code mustbe rotated around Boolean lattice by the distance 3 in the anticlockwise direction shown in FlG. 5 so as to bring the code (00111) in coincidence with the code (00000).

Assuming that a code is a vector composed of signals a to e in the present invention, when a specific code III a (a,,, b,,, c,,, d,,, e,,) is reset to make it the origin and the displacement or condition proceeds fromthis origin to an optical code I!) (a, b, c, d, e) a parity vector P ID 0 69 D is produced in accordance with the following definition and a cyclic transposition or substitution 1r which is determined in relation to ll) is effected with respect to the parity vector [P so that a new code 1r [P of the vector isproduced thereby permitting the amount of displacement to be obtained by thecode rrlP. The

lP=ll),,aall) =[P (a q) a, b a; b, c o c, d orbe oe) where:

6) exclusive or In other words,

The cyclic transposition or substitution 11- is a function of the vector D at the reset position.

1r is represented in the positive domain as follows: 1r+ W (like a,,) where W represents the weight of the vector (ll) 19 a,,) and is equal to the number of the components of the vector which are in the condition 1.

11+ shown in FIG. 4 shows the cyclic transposition in the positive domain, while 1r" shows the cyclic transposition in the negative domain.

For example, one cyclic transposition effected to the vector (a, b, c, d, e) in the positive domain means that the vector is converted to a vector (e, a, b, c, d).

Some examples will be described below.

Example 1 The origin is set to 0 When the displacement advances by three units in the positive sense so as to reach ll)=(llll0),

The cyclic transposition 1r is represented as fol- Therefore, the parity vector P (11001) is cyclically transposed by three times 1r+ 3) as follows:

E: 11001 (11101) 01110 ooii 1 1r+ [P (001 ll) This 'vector (0011 1) indicates the unit 3", Le, the correct value of 3 instead of 6" is indicated when the origin is set to unit 3 and the condition or the displacement advances by three units in the positive sense. Example 2 The origin is set D, (l l 1 l0) (D, 6) and the condition or the displacement advances by seven units in the positive sense, thus (D 3) Then P (l lOOl and 11+ W (I), 9 a,)

Therefore, one cyclic transposition is effected to the parity vector P 1r+lP= (11100) This vector 1r-llP correctly indicates that the amount of displacement is 7 units. I Example 3 The origin is set to e (D 6) The displacement advances in the positive sense by one unit to reach The parity vector IP and 1r+ are By effecting one cyclic transposition to 1r+ P: (0000l) l This vector indicates that the amount of displacement is one unit.

As described above, the cyclic transposition 1r is given as follows when the condition or displacement advances in the positive sense 1r+ W (Dem FIG. 4 shows this value 1r+. As seen in FIG. 4, the value 11+ returns to the original value when the cyclic transposition is effected five times. Therefore, the value D+ may be substituted for the value 1r+.

FIG. 6 shows an example of the division logic circuit of the present invention in which the units 0-9 are indicated-depending upon the specific combination of the conditions of five signals a-e shown in FIG. 4.

In FIG. 6, the signals a-e are applied to flip-flop circuits FF to FF respectively, and, at the same time, the signals a-e are supplied to exclusive or" circuits EOR to EOR respectively. The output each of the flip-flop circuits FF -FF: is supplied to the other input terminal of the respective exclusive or circuit EOR EOR, as shown. A reset signal line for setting the origin is connected to the trigger terminal-each of the flip-flop circuits FF,-FF Thus, when the reset signal is applied'to the flip-flop circuits FF,-FF the state of the combination of the conditions of the signals ae existing in the flip-flop circuits FF -FF at the moment the reset signal is applied thereto can be memorized therein. This means that the conditions of the respective signals a-e as set to the origin (11], (a,,, b,,, c d,,, e,) are memorized in the flip-flop circuits FF,FF,,.

Thus, the respective components or parameters of the codell), (a 1),, c,,, d,,, e memorized in the flipflop circuits FF,FF, at the reset position and the respective compo-nents or parameters of the veetorD= (a, b, c, d, e) are supplied to the exclusive or circuits EOR,-EOR so that the components of the parity vectorIP =lll lll (a ea a, b, ea b, c o c, d,,e d, 12,9 e) are obtained at theoutputs of exclusive or circuits EOR- -EOR, respectively. Theoutput of the"exclusive or" circuits EOR EOR representing the respective components of the parity vector [P are supplied to cyclic transposition or substitution circuit Err as shown.

Exclusive or circuits EOR -EOR, are provided in order to obtain the cyclic transposition 1r+ in the positive domain. One of the input terminal each of the exclusive or circuits EOR EOR is commonly con nected together to the output terminal of the flip-flop circuit FF while the other input terminal of the respective exclusive or circuits EOR EOR is connected to the output terminal of the respective flip-flop circuits FF -FF Each of the exclusive or circuits EOR EOR indicates one cyclic transposition or substitution when the output thereof is logic I. The

number of the outputs obtained from the exclusive or circuits EOR EOR which are logic 1 represents the total cyclic transposition 1r+ and the thus obtained total cyclic transposition 7r+ is supplied to the cyclic transposition circuit Err so as to control the times or the number the transposition is effected to the parity vector P.

FIG. 7 shows the detail of the cyclic transposition circuit Err. In the embodiment of FIG. 6, the maximum number of times the cyclic transposition is effected is four, so the cyclic transposition circuit Err suffices to include four single cyclic transposition circuits 1r -qr and these single cyclic transposition circuits rr -rr, are connected in cascade connection. The output of each of the exclusive or circuits EOR -EOR, is connected to the respective single cyclic transposition circuits m-m while the parity vector-P is supplied to the circuit Zn as shown so that a cyclic transposition is effected in any of the single cyclic transposition circuits 77 -17 to which the output of logic l"0 is supplied from the exclusive or" circuit connected thereto thereby permitting the output converted so as to be made the re- An embodiment for obtaining the above outputs a'-e' is shown in FIG. 9. In FIG. 9, two input and gates AND -AND are provided, and one of the input terminals each of the and gates" AND,-AND;-, issupplied with the input signals a, b, c, d, e, respectively while the cyclic transposition signal 1r+ is supplied commonly to the other input terminal each of the and gates AND- ,AND Two input and gates" AND -ANDm are further provided, and one of the input terminals each of the and gates AND AND is supplied with the input signals a, b, c, d, 2, respectively while inverted cyclic transposition signal 7 obtained through inversion circuit I 1 from the cyclic transposition signal 1r is supplied commonly to the other input terminal each of the and gates AND AND The output terminals of and gates AND; and AND are connected to the input terminals of or gate" OR, and the output tenninals of the and gates" AND, and AND, are connected to the input terminals of or gate" OR,, the output terminals of the and gates" AND, and AND, being connected to the input terminals of of gate" OR,, while the output terminals of the and gates" AND, and AND are eonnected'to the input terminals of or gate" OR, and'the'output termi- I nals of "and gates" AND, and AND are connected to the input terminals of or gate" OR, as shown in FIG.

By the connection of the circuit of FIG. 9, it is apparent that the output signals a, b; c',- d, e as defined above are obtained from the input signals a, b, c, d, e.

out any cyclic transposition effected thereto.

i.e., the input signal is directly given to the output with The output (a', b, c, d, e') of the cyclic transposi tion circuit 211' is then supplied to discriminating circuit R as shown in FIG. 6 so that the combination of the conditions of the signals a, b, c, d, e is discriminated therein so as to obtain the value D.

FIG. 10 shows an embodiment of the discriminating circuit R. The output signals a, b', c, d, e of the or gates" OR,-OR,, are supplied to the discriminating-circuit R while it is supplied-with sign input S which is indicative of the displacement in the positive sense or in the negative sense. The sign input S isproduced as described later, and it is made logic 1 when the displacement advances in the positive domain, while it is domain can be indicated by an absolute value. In other words, when. the displacement proceeds in. the negativedomain, the value having negative sign suchas 1, -2, 3 as measured from the origin can be indicated.

The positive sign input S and the'negative sign input S are generated as shown in FIG. 11, for exampleThe circuit shown in FIG. 11 includes a zerodetectingcircuit 2 which is adapted to detect the condition in which I is selected to'be shorter than the time in which the condition varies by 9 units, then the output of the and gate,AND will be 0 as indicated by d in FIG. 12. On the other hand, an instantaneous pulse indicated by" e in FIG; 12is obtained by differentiating the rise of the zero detection signal a by the differentiation circuit which is supplied tothe set inputterminal S thereof so that a positive sign input S is obtainedfrom-the set output terminal 0 of the flip-flop circuit FF,

When the-conditionisvarying in the negative sense,

logic: product or logic and of the output D5, and the delayed signal bis made l asindicated by h in FIG.

1-2. Therefore, the flip-flop circuit FF, is reset by the, output h of the andgate"'AND after it has been set by the-output pulse e of the differentiation circuit DEF,

sothat the negative sign S is supplied from the reset output terminal Q of the flip-flop circuit FF,.

Various circuits for generating the positive and negative sign S and S are available other than that shown in FIG. '11.

FIGS. l'3 and 14 show an exampleof the shifting-up of the figure in the number counted in theelectronic counter. Two delay circuits D5 and Dg and two and Thus, the amount of the displacement from these 7 origin ineither of the positive domain and the negative gates AND andAND are provided. Output D, of the discriminating circuit R representing 91 unit is applied to the delay circuit D, so that the output thereof is delayed by a short time t Theoutput of the delay 1 circuit D, is supplied ftothe and gateAND' The all the figures of the number counted in the electronic counter as well as all the outputs D -D,, of the discriminating circuit R are made zero. The output terminal of the zero detecting circuit Z is connected to one of the input terminals of and gate" AND through'adelay circuit D interconnected therebetween, while the other input terminal of the and gate AND is supplied with the output Dg of the discriminating circuit R. The output of the andgate AND is connected to reset input terminal R of flip-flop circuit FF while the set input terminal S of the flip-flop'circuit FF is connected to the output terminal of the zero detectingcircuit Z through a differentiation circuit DEF interconnected therebetween. As described above, an 'output is generated in the zero detecting circuit Z when all the outputs of the electronic counter and the discriminating circuit R are made zero. Thus, it indicates that the condition reaches the origin. FIG. 12 shows theoperation of the circuit of FIG. 11. The zero detection-signal of the zero detecting circuit Z is indicated by a in FIG.

12. The output b of the delay circuit D, is shown asoutput D, is directly'supplied to the and gate AND Q The output D of the discriminating circuit R representing the 0 unit is supplied to "the delay circuit D}, so

thatthe output thereof is delayed by the short time t',. The output of the delay circuit D is supplied to the played in the electronic counter varies in the positive 'sense or in the addition mode at the absolute value thereof, the output D is generated by the discriminating circuit R after the output D, has been generated.

The output D and theout'put D are indicated, by a and 14; respectively. Therefore, the shifting-up pulse for increasingthe absolute value of thenumber'dis'played in the electronic-counter isgenerated by the and gate AND as'indicated by e in FIG. 14, whereas no output being delayed by the time t, from-the output a of the:

zero detecting circuit 2. The output D, supplied to the and gate AND from the discriminating circuit R when the condition is varying in the positive senseappears after the condition varies from the zero conditionby 9 units as shownby c inFIG. 12. If the delay time is generated in the and" gateAND}, as shown by f in When the con'dition varies'in the sensein which the' number displayed in the electronic counter is dee' creased at the absolute value thereof,theoutput'D isgeneratedby the discriminating circuit R after the'outputD has been generated. Therefore, no output is gem erated by the and" gate AND whereas the shifting.- up pulsefor decreasing the absolute value "displayed in theelectronic counter is generatedby the "and gate AND The additionshifting-up pulse or the subtraction shifting-up pulse is supplied to' the electronic counter so asto permit the second to last figure and the preceding figure in the number counted in the electric counterto be displayed. 

1. A division logic circuit in which a number represented by a specific combination of bits in a digital signal, only one bit of which is changed at a time, is convertEd into a number which is measured from an origin selected by an optional combination of the bits in the signal, wherein the improvement comprises: a memory circuit for memorizing the combination of bits in the signal to be used for the origin; a parity counting circuit for producing first parity signals from logical operations performed on corresponding bits of the digital signal stored in the memory circuit and the digital signal to be converted; a marking bit counting circuit for producing a second parity signal in accordance with a predetermined marking bit position; a weight counting circuit, connected to said parity counting circuit, for determining the weight to be accorded to the parity of said first parity signals; and a conversion circuit, connected to said weight counting circuit and to said marking bit counting circuit for combining the bits of the signal to be converted on the basis of the weight of the first parity signals and the second parity signals as determined from the predetermined marking bit position, the thus obtained combination being indicative of the desired number measured from the origin.
 2. A division logic circuit in which a number represented by a specific combination of bits in a digital signal, only one bit of which is changed at a time, is converted into another number which is measured from an origin selected by an optional combination of the bits in the signal, wherein the improvement comprises: a memory circuit comprising a plurality of flip-flop circuits for memorizing the combination of bits in the signal to be used as the origin, one flip-flop circuit being provided for each bit in the digital signal to be converted, said flip-flop circuits receiving in common a reset signal for memorizing the bits of the signal to be utilized as the origin; a parity circuit comprising a first plurality of ''''exclusive -or'''' circuits for producing ''''exclusive - or'''' outputs from corresponding bits in the signal stored in the memory circuit and the signal to be converted, to yield the number measured from the selected origin, one ''''exclusive - or'''' circuit being provided for each bit in the digital signal to be converted, each ''''exclusive - or'''' circuit receiving one bit of the signal to be converted and the output from the corresponding flip-flop circuit; a cyclic transposition circuit comprising a plurality of single transposition circuits connected in cascade for effecting cyclic transposition in the bits of the output signal from said parity circuit in regular order, the number of single transposition circuits being one less than the number of bits in the digital signal to be converted; and a control circuit comprising a second plurality of ''''exclusive -or'''' circuits for producing a control signal from the bits of the digital signal stored in said memory circuit to actuate said cyclic transposition circuit, the number of ''''exclusive -or'''' circuits in said second plurality being one less than the number of bits in the signal to be converted, each ''''exclusive - or'''' circuit in said second plurality receiving in common the output of a first one of said flip-flop circuits and, exclusively, the output of another one of said flip-flop circuits, the outputs of said second plurality of ''''exclusive -or'''' circuits being connected to said single transposition circuits, respectively. 